By Stephen Nellis
(Reuters) – Synopsys Inc on Wednesday rolled out new artificial intelligence tools designed to get better results faster in the various stages of designing computing chips.
Synopsys makes software that companies use to design computing chips. Modern chips have tens of billions of tiny on-off switches called transistors, and their precise arrangement on the chip has a big impact on the chip’s cost and performance, so designers use software from companies like Synopsys to help.
Synopsys first released an AI tool for one part of the chip design process three years ago, and with customers like Samsung Electronics Co Ltd and ST Microelectronics using the system.
The tools Synopsys released Wednesday at its annual user conference in Santa Clara, California, spread much further across the chip design process. They are aimed at helping engineers hunt for bugs in their designs, test physical sample chips from manufacturing partners and, once mass production has begun, boost the proportion of defect-free chips coming off the production line.
Synopsys also on Wednesday released a tool to make it easier to move analog chip designs from one manufacturing partner to the other. Such moves have traditionally been expensive and time-consuming.
Sassine Ghazi, president and chief operating officer of Synopsys, said that the dual hit of a chip supply chain crunch and U.S. export controls on doing business has chip executives looking for more options.
“Every CEO was looking for an alternative. Nobody wants to be caught off guard if someone says you cannot use the Chinese or Taiwanese,” Ghazi said.
Synopsys is in a race with Cadence Design Systems, its largest competitor, to add AI to chip design software. While some of the Synopsys tools released Wednesday are catching up to Cadence, Karl Freund, principal analyst with Cambrian AI research, said Synopsys is ahead, with more than 100 chips by customers using its AI tools coming to market.
“They definitely lap Cadence, especially if you look at what’s happened with physical design,” Freund said. “I think they’ll probably be at 1,000 (completed chip designs) by the end of the year.”
(Reporting by Stephen Nellis in San Francisco; editing by Jonathan Oatis)
Disclaimer: This report is auto generated from the Reuters news service. ThePrint holds no responsibilty for its content.
Source: The Print
